1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
2. Description of the Related Art
FIGS. 14A to 14D are views for explaining a method of manufacturing a vertical NPN transistor as an example of a semiconductor device.
First, as shown in FIGS. 14A and 14B, selective ion implantation or thermal diffusion using a P-type impurity (e.g., boron B.sup.+) is performed to form a base region 100. As shown in FIGS. 14B and 14C, an emitter region 101 is formed by selective ion implantation or thermal diffusion using an N-type impurity (e.g., arsenic As.sup.+). After this formation of the emitter region 101, a P-type impurity (e.g., boron B.sup.+) is selectively ion-implanted or thermally diffused again in a contact region of the base region 100 to form an inner base region 102, as shown in FIGS. 14C and 14D.
When the vertical NPN transistor is to be formed by the above conventional manufacturing method, however, a patterning (to be referred to as lithography hereinafter) step using a photosensitive resin (to be referred to as a resist hereinafter) must be performed when the base region 100, emitter region 101, and inner base region 102 are formed, respectively. As a result, the manufacturing time and cost are increased. In addition, an alignment shift in lithography must be taken into consideration, which limits a reduction in device size.
Such a problem similarly arises in forming N- and P-well layers, in forming N- and P-buried layers, and in forming N- and P-diffusion layers.